The present invention relates to microelectronics and, in particular, to a method of fabricating an ultra-shallow junction in Field Effect Transistor (FET) devices, such as Complementary Metal Oxide Semiconductor (CMOS) devices.
Advances in the miniaturization of CMOS devices have been a key driving force behind the explosive growth of various network centric computing products such as ASIC high speed microprocessors and memories, low power hand-held computing devices, cable modems and advanced multi-media audio and video devices. Smaller CMOS devices typically equate to faster switching times which led to speedier and better performing end user systems.
The process of miniaturizing CMOS devices involves scaling down various horizontal and vertical dimensions in the CMOS device structure. In particular, the thickness of the ion implanted source/drain junction of a p- or n-type transistor is scaled down with a corresponding scaled increase in the substrate channel doping. In this manner, constant electric field is maintained in the transistor channel which results in higher speed performance for the scaled down CMOS transistor. For example, for a 0.1 xcexcm CMOS device, the source/drain extension junction closest to the transistor channel is as shallow as 50 nm and has a channel doping concentration as high as 1xc3x971018/cm3.
For CMOS devices with a critical gate dimension below 0.25 xcexcm, a shallow junction is not the only requirement. A more important requirement, in the source/drain extension junction, is the abruptness of the junction/dopant profile slope which is in proximity to the transistor channel. As shown in FIG. 1(a), there is more penetration of the source/drain dopant into the transistor channel as the junction/profile slope becomes less abrupt. This results in poor threshold voltage roll-off characteristics for sub-quarter micron CMOS devices (See, for example, FIG. 1(b)). Thus, for small advanced CMOS devices, it is vital for the source/drain extension junction profile to be shallow, abrupt and have a high surface concentration.
The formation of source/drain extension junctions in CMOS devices is commonly carried out in the prior art by ion implantation in appropriately masked source/drain regions of a silicon substrate with boron (p-type) or arsenic and phosphorous (n-type) dopants. To minimize ion channeling during ion implantation, which will broaden the implanted profile, the silicon substrate is usually preamorphized with heavy ions such as Ge or Si. Preamorphization of silicon is a process in which sufficient ion dose is used to convert the surface region of the Si substrate from crystalline to amorphous. The depth of the converted amorphous region depends on the nature of the ions, ion energy and the dose of the incident ions on the silicon substrate. Although the preamorphization process helps to sharpen the implanted profile and improve the epitaxial silicon regrowth process during subsequent thermal annealing, it also creates extensive crystal damage and excess Si interstitials at the End of Range (EOR) of the preamorphized ions. As is known to those skilled in the art, Si interstitials are displaced Si atoms created by ion bombardment of the crystalline Si substrate. During thermal annealing, the presence of these EORs is detrimental since excess Si interstitials greatly enhance (10 to 1000 times) the normal diffusion of dopants through the Si substrate and result in a much deeper source/drain junction and poorer junction profile.
This greatly enhanced diffusion of dopants due to the presence of excess Si interstitials around the dopant atoms is commonly referred to in the prior art as transient enhanced diffusion (TED). In particular, the relatively high diffusivity of small boron dopants in combination with ion channeling and transient diffusion makes the fabrication of small p-type CMOS devices difficult. The aforementioned combination also represents a major hurdle that needs to be overcome before further miniaturization of the CMOS device technology can occur.
Several prior art approaches have attempted to reduce the transient enhanced diffusion for shallow junction formation. In one approach, a carbon co-implant was used to reduce the transient diffusion of boron dopant during rapid thermal anneal (RTA). The conditions employed in forming the shallow junction using carbon co-implantation were as follows: 2 keV boron shallow implant, dose 1xc3x971015/cm2, carbon implant (energy not reported), dose=2xc3x971014/cm2. Rapid thermal anneal (RTA) conditions were 950xc2x0 C., 30 seconds, or 1050xc2x0 C., 30 seconds, respectively. Although carbon co-implant is effective in reducing the transient diffusion of boron, this method suffers from the disadvantage that high density of residual defects remain after RTA. This is the case even using high temperature anneal conditions (1050xc2x0 C., 30 seconds). The high density of residual defects results in high electrical leakages for the shallow junction.
Another approach reported by T. H. Huang et al. (xe2x80x9cInfluence of Fluorine Preamorphization on the Diffusion and Activation of Low-energy Implanted Boron during Rapid Thermal Anneal,xe2x80x9d Appl. Phys. Lett., (1994) Vol. 65, No. 14, p. 1829) used fluorine co-implants to reduce the transient diffusion of boron dopants during rapid thermal anneals. The conditions used in this reference for shallow junction formation are as follows: fluorine implant, 40 keV ion energy, dose=2xc3x971015/cm2, 5 keV boron or 23 keV BF2 shallow implants. In the process disclosed by Huang et al., the wafers were rapid thermal annealed at 1000xc2x0 C., 1050xc2x0 C. and 1100xc2x0 C. for 30 seconds. Although the presence of fluorine implants reduced the transient boron enhanced diffusion during RTA, this prior art method also suffers from the disadvantage that residual defects remain after 1000xc2x0 C., 30 seconds anneal. Residual defects can only be removed with 1100xc2x0 C., 30 seconds anneal. However, substantial dopant motion occurs at this higher temperature and therefor ultra-shallow junctions cannot be formed.
Another approach reported by S. Saito entitled xe2x80x9cDefect Reduction by MeV Ion Implantation for Shallow Junction Formation,xe2x80x9d Appl. Phys. Lett., (1993) Vol. 63, No. 2, p. 197 used fluorine implants for preamphorization (40 kev, 1xc3x971015/cm2), shallow implant; boron at 10 keV and 5xc3x971015/cm2. This was followed by ion implantation of either fluorine or silicon at 1 MeV energy or arsenic at 2 MeV energy. The dose used for the MeV implant was between 5xc3x971014 to 5xc3x971015/cm2. The samples were rapid thermal annealed at 1000xc2x0 C. or 1100xc2x0 C. for 110 seconds. Under these experimental conditions, Saito demonstrated that the MeV implants were effective in reducing the boron transient diffusion with and without fluorine preamphorization. This reference also demonstrated that maximum reduction in boron dopant diffusion was achieved when both fluorine preamorphization and Mev fluorine implants were used. However, as mentioned in the prior art earlier, use of fluorine implants creates residual defects and requires temperatures as high as 1100xc2x0 C. for low leakage junction to be formed.
In each of the prior art references mentioned hereinabove, high energies were used to implant boron (2 to 10 keV) or BF2 (23 keV) into semiconductor materials. These energy ranges are however unsuitable to create an ultra-shallow boron dopant junction below 50 nm. All the junction depths created by the prior art techniques are between 60-100 nm. Although the combination of high temperature ( greater than 1000xc2x0 C.) and long annealing times (10 to 30 seconds) minimize residue defects due to carbon or fluorine co-implants, it inhibits the formation of ultra-shallow junctions. Moreover, all of the prior art techniques overlook the importance of the rate at which the wafer reaches the desired anneal temperature, i.e., 1000xc2x0 to 1100xc2x0 C., as well as ramp down rate for the wafer to cool down from the anneal temperature. Despite the current advances made in the field of microelectronics, there is still a need for providing a new and improved method which provides an ultra-shallow junction in FET devices while overcoming all of the drawbacks mentioned hereinabove.
One object of the present invention is to provide a method of fabricating ultra-shallow junctions in microelectronic devices.
Another object of the present invention is directed to providing a method wherein all of the aforementioned drawbacks of the prior art processes have been overcome.
A further object of the present invention is to provide a method wherein the resultant microelectronic device has a shallow extension junction whose boundaries exhibit a sharp change in dopant concentration.
These as well as other objects and advantages are achieved by the method of the present invention wherein an ultra-shallow junction is formed in a semiconductor material by using a high energy ion implantation step followed by low energy implantation of a dopant ion and subsequent annealing. Specifically the present invention relates to a method of forming an ultra-shallow junction in a semiconductor material comprising the steps of:
(a) irradiating a surface of a semiconductor material with a first ion at a first irradiation energy sufficient to implant said first ion to a first depth;
(b) irradiating said semiconductor surface with a dopant ion at a second irradiation energy sufficient to implant said dopant ion to a second depth that is less than said first depth of said first ion; and
(c) heating said semiconductor material under conditions effective to cause substantial annealing of said dopant ion within said semiconductor material and for a period of time to prevent substantial diffusion of said dopant ion to a depth greater than said second depth.
According to a preferred embodiment of the present invention, and prior to conducting step (b), the semiconductor surface is irradiated with a second ion at a third irradiation energy which is sufficient to render said semiconductor material substantially amorphous and to a third depth greater than said second depth and less than said first depth.
Another preferred embodiment of the instant invention comprises forming a thin layer of amorphous insulator material on said surface of said semiconductor material. When this embodiment of the present invention is carried out, it typically occurs prior to conducting step (a) or (b).
In yet another embodiment of the present invention, step (b) may precede step (a). That is, the present method may be carried out by conducting step (b) before step (a), i.e., by irradiating with the dopant ion first, followed by irradiating with a high energy deep implant of the first ion.
Preferably, the semiconductor material is silicon and the first irradiation energy, for the high energy deep implant, is between about 200 keV and about 2000 keV, and the second irradiation energy, for shallow dopant implantation is between about 100 eV to about 5 keV.
In another aspect of the present invention, a structure useful in fabricating microelectronic devices such as a FET or CMOS device is provided. In accordance with this aspect of the present invention, a structure having an abrupt p-n junction is disclosed. The structure comprises a shallow implant region defined by dopant material of a first conductivity type formed in the surface of a semiconductor substrate of a second conductivity type, said semiconductor substrate comprises a region of coalesced high concentration of interstitial first ions disposed substantially at a first depth, said shallow implant region having a second depth less than said first depth wherein the concentration of said dopant ion at a boundary junction of said shallow implant region with said semiconductor substrate changes by a factor of 10 within a distance of less than 60 xc3x85 measured at, and perpendicular to, said boundary.
A field effect transistor comprising a micro-electronic device having a source region and a drain region formed in mutually spaced adjacency in said surface of a semiconductor substrate having a pair of said shallow implant regions being disposed between and formed as spaced-apart extensions of source and drain regions to form a channel region between the spaced-apart shallow implant regions, and a gate electrode overlying said channel region is also provided herein.